The formation of metal patterns, which are used for interconnecting integrated circuit devices on semiconductor substrates, often involves the process of forming a dielectric layer, forming openings in the dielectric layer, filling the openings with a metallic material, and polishing the metallic material. After the polishing, the excess portions of the metallic material outside the openings are removed. The remaining metallic material in the openings thus forms contact plugs, vias, metal lines, or the like.
In the etching step for forming the openings and the subsequent polishing processes (which are sometimes chemical mechanical polish (CMP) processes), the pattern density difference of the metallic material in different regions causes the micro-loading effect, and the manufacturing yield may be adversely affected. For example, in the formation of contact plugs that are connected to the source and drain regions of transistors, there may be a difference in the pattern density of the contact plugs. The difference may cause the excess removal of the etch stop layer, which is used for forming the contact plugs.